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ICs for Communications
Multichannel Network Interface Controller for HDLC + Extensions MUNICH128X PEB 20324 Version 2.2
Hardware Reference Manual 04.99
DS 1
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PEB 20324, PEF 20324 Revision History: Previous Version: Page Page (in previous (in current Version) Version) Chapter 6 Chapter 5 Current Version: 04.99 Product Overview 12/97 DS3 Subjects (major changes since last revision)
Updated. Pin Description Tables updated.
Tables 1...8 Tables 2-1 ...2-8
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com
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PEB 20324 PEF 20324
Preface
The MUNICH128X is a 128-channel WAN Protocol Controller which provides four independent 24/32-channel HDLC controllers, each with a dedicated 64-channel DMA Controller and a Serial PCM Interface Controller. The device is offered in a 160pin MQFP package, making it ideal for high-port-density applications. Organization of this Document This Hardware Reference Manual is divided into 7 chapters. It is organized as follows: * Chapter 1, Introduction Gives a general description of the product and its family, lists the key features, and presents some typical applications. * Chapter 2, Pin Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. * Chapter 3, Functional IC Description Gives a general functional overview of the MUNICH128X. * Chapter 4, Electrical Characteristics Gives a detailed description of all electrical DC and AC characteristics and provides timing diagrams and values for all interfaces. * Chapter 5, Test Modes Gives a detailed description of the JTAG boundary scan interface. * Chapter 6, Package Outline
Related Documentation MUNICH128X Version 2.2 Prpgrammer's Reference Manual 03.99 DS1
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Table of Contents Page
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1 1.1 1.2 1.3 1.4 2 2.1 3 3.1 3.2 3.3 3.4 4 4.1 5 5.1 5.2 5.3 5.4 5.5 5.6 5.6.1 5.6.1.1 5.6.1.2 5.6.1.3 5.6.2 5.6.3 5.6.4 5.6.5 6 6.1 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Differences to the MUNICH32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Important Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 PCI Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 PCI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 De-multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Boundary Scan Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
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List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 1-4 Figure 2-1 Figure 3-1 Figure 3-1 Figure 3-2 Figure 5-1 Figure 5-2 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Figure 5-10 Figure 5-11 Figure 6-1 Page
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 System Integration of the MUNICH128X in PCI-Based System . . . . . .12 System Integration of the MUNICH128X in De-multiplexed System . . .13 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 System Integration of the MUNICH128X in PCI-Based System . . . . . .34 System Integration of the MUNICH128X in De-multiplexed System . . .35 Power-up and Power-down scenarios . . . . . . . . . . . . . . . . . . . . . . . . . .37 Power-Failure scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . . .43 PCI Output Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . .44 PCI Input Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . . .44 PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 PCI Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Master Single READ Transaction followed by a Master Single WRITE Transaction in De-multiplexed Bus Configuration . . . . . . . . . . .51 Master Burst WRITE/READ Access in De-multiplexed Bus Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . .57
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List of Tables Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 5-1 Table 5-2 Table 5-3 Page 17 18 19 20 21 25 26 27 39 39
Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 6-1 Table 6-2
Pin Descriptions by Functional Block: Port 0 Serial Interface . . . . . . . Pin Descriptions by Functional Block: Port 1 Serial Interface . . . . . . . Pin Descriptions by Functional Block: Port 2 Serial Interface . . . . . . . Pin Descriptions by Functional Block: Port 3 Serial Interface . . . . . . . Pin Descriptions by Functional Block: PCI Interface . . . . . . . . . . . . . . Pin Descriptions by Functional Block: DEMUX Interface (additional signals to PCI Interface) . . . . . . . . . . . . Pin Descriptions by Functional Block: Power Supply. . . . . . . . . . . . . . Pin Descriptions by Functional Block: Test Interface . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-PCI Interface Pins TA = 0 to + 70xC; VDD5 = 5 V 5%, VDD3 = 3.3 V 0.3 V, VSS = 0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-PCI Interface Pins TA = 25xC; VDD5 = 5 V 5%, VDD3 = 3.3 V 0.3 V, VSS = 0 V . . . PCI Input and Output Measurement Conditions . . . . . . . . . . . . . . . . . Number of Wait States Inserted by the MUNICH128X as Initiator. . . . Number of Wait States Inserted by the MUNICH128X as Slave . . . . . PCI Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCI Interface Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . Additional De-multiplexed Interface Signal Characteristics . . . . . . . . . PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary Scan Sequence in MUNICH128X . . . . . . . . . . . . . . . . . . . . Boundary Scan Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41 42 44 48 48 49 50 52 54 55 56 58 62
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Introduction
1
Introduction
The MUNICH128X is a 128-channel WAN Protocol Controller which provides four independent 24/32-channel HDLC controllers, each with a dedicated 64-channel DMA Controller and a Serial PCM Interface Controller. The device is offered in a 160pin MQFP package, making it ideal for high-port-density applications. The MUNICH128X provides capability for up to 128 full duplex serial PCM channels. The chip performs layer 2 HDLC formatting/deformatting or V.110 or X.30 protocols up to a data rate of 38.4 kbit/s (V.110) or 64 kbit/s (HDLC). The MUNICH128X also performs transparent transmission for DMI modes 0, 1, and 2. Processed data is transferred to host memory via the PCI interface or de-multiplexed bus interface. The MUNICH128X is compatible with the LAPD ISDN (Integrated Services Digital Network) protocol specified by CCITT, as well as with HDLC, SDLC, LAPB and DMI protocols. It provides rate adaptation for time slot transmission from 64 kbit/s down to 8 kbit/s and the concatenation of time slots, supporting the ISDN H0, H11, H12 superchannels.
PCM
PCM
PCM
PCM
Serial Interface
Serial Interface
Serial Interface
Serial Interface
Protocol Controller
Protocol Controller
Protocol Controller
Protocol Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
PCI Interface/DEMUX BUS
Address/Data
Control
ITB10007
Figure 1-1
Simplified Block Diagram
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Multichannel Network Interface Controller for HDLC + Extensions MUNICH128X
Version 2.2
PEB 20324
CMOS
1.1
Features
PCM
Four independent 24/32-channel HDLC Controllers with common PCI interface. Each of them provides: * Dedicated 1024 byte Tx Buffer * Dedicated 1024 byte Rx Buffer * Dedicated Serial PCM Interface Controller - T1 rates: 1.536, 1.544, 3.088, 6.176 Mbit/s - E1 rates: 2.048, 4.096, 8.192 Mbit/s * Dedicated 64-channel DMA Controller - Supports linked-list buffer processing - 16-DWord Tx DMA FIFO - 16-DWord Rx DMA FIFO - 4-DWord burst of Rx descriptors - 3-DWord burst of Tx descriptors
P-MQFP-160-1
- n-DWord burst of configuration blocks (n is unlimited according the MUNICH128X, but internal port arbitration may lead to a lower typical burst size of 4 or 8 DWords) * Dynamic Programmable Channel Allocation - Compatible with T1/DS1 24-channel and CEPT 32-channel PCM byte format - Concatenation of any, not necessarily consecutive, time slots to superchannels independently for receive and transmit direction - Support of H0, H11, H12 ISDN-channels - Subchanneling on each time slot possible
Type PEB 20324 PEF 20324
Hardware Reference Manual 8
Package P-MQFP-160-1 P-MQFP-160-1
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Introduction * Bit Processor Functions (adjustable for each channel) - HDLC Protocol - Automatic flag detection - Shared opening and closing flag - Detection of interframe-time-fill change, generation of interframe-time-fill `1's or flags - Zero bit insertion - Flag stuffing and flag adjustment for rate adaption - CRC generation and checking (16 or 32 bits) - Transparent CRC option per channel and/or per message - Error detection (abort, long frame, CRC error, 2 categories of short frames, non-octet frame content) - ABORT/IDLE flag generation - V.110/X.30 Protocol - Automatic synchronization in receive direction, automatic generation of the synchronization pattern in transmit direction - E/S/X bits freely programmable in transmit direction, may be changed during transmission; changes monitored and reported in receive direction - Generation/detection of loss of synchronism - Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s - Transparent Mode A - Slot synchronous transparent transmission/reception without frame structure - Flag generation, flag stuffing, flag extraction, flag generation in the abort case with programmable flag - Synchronized data transfer for fractional T1/PRI channels - Transparent Mode B - Transparent transmission/reception in frames delimited by 00H flags - Shared opening and closing flag - Flag stuffing, flag detection, flag generation in the abort case - Error detection (non octet frame content, short frame, long frame) - Transparent Mode R - Transparent transmission/reception with GSM 08.60 frame structure - Automatic 0000H flag generation/detection - Support of 40, 391/2, 401/2 octet frames - Error detection (non octet frame contents, short frame, long frame) - Protocol Independent - Channel inversion (data, flags, IDLE code) - Format conventions as in CCITT Q.921 2.8 - Data over- and underflow detected
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Introduction * * * * * 32 Bit / 33 MHz PCI 2.1 Interface 32 Bit / 33 MHz De-multiplexed Bus Interface Option 0.5 m, 3.3 V-Optimized Technology 3.3 V I/O Capability with 5.0 V Input Tolerance 160-pin MQFP Package
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Introduction
1.2
*
Logic Symbol
JTAG Test Interface TCK TMS TDI TDO TRST TEST VSS VDD3 VDD5 AD(31:0) C/BE(3:0) PAR FRAME IRDY TRDY STOP IDSEL DEVSEL PERR SERR REQ GNT CLK RST INTA
TxD0 RxD0 TSP0 RSP0 TXDEN0 TxCLK0 RxCLK0 Serial Channel 0 (PCM0) Serial Channel 1 (PCM1) Serial Channel 2 (PCM2) Serial Channel 3 (PCM3)
PCI BUS
MUNICH128X PEB 20324 PEF 20324
A(27:2) DPCI(1:0) W/R (de-multiplexed address bus)
Control and Address Bus Extension for De-multiplexed Bus Interface
Figure 1-2
Logic Symbol
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Introduction
1.3
Typical Applications
The MUNICH128X provides protocol processing and host memory buffer management for four independent T1/E1 PRI ports. As such, the MUNICH128X fits into a system between the framer or LIU/framer devices (e.g., the Siemens FALC(R)54/FALC(R)54-LH transceiver) and the host bus (e.g. PCI Bus), as illustrated in Figure 1-3. The MUNICH128X provides four independent Serial PCM ports which connect directly into the framer devices. In PCI based systems a dedicated microcontroller or PCI bridge chip is necessary to configure the framer or LIU/framer devices. Additionally, the MUNICH128X provides a PCI 2.1 interface which connects directly to the system PCI bus. Optionally, this bus can be configured in De-multiplexed Mode.
T1/E1/PRI
T1/E1/PRI
T1/E1/PRI
T1/E1/PRI
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
Dedicated CPU
MUNICH128X
PCI BUS
PCI Bridge Chip
Host Memory
Processor
ITS10009
Figure 1-3
System Integration of the MUNICH128X in PCI-Based System
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Introduction
T1/E1/PRI
T1/E1/PRI
T1/E1/PRI
T1/E1/PRI
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
MUNICH128X
Glue Logic
De-multiplexed BUS
Processor
Host Memory
ITS10010
Figure 1-4
System Integration of the MUNICH128X in De-multiplexed System
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Introduction
1.4
Differences to the MUNICH32
* 128-channel capability * Symmetrical Rx and Tx Buffer Descriptor formats for faster switching * Improved Tx idle channel polling process for significantly reducing bus occupancy of idle Tx channels * Dedicated 1024 byte Tx Buffer * Dedicated 1024 byte Rx Buffer * Burst capability also on transmit and receive data sections (8 DWORDs) * Additional PCM modes supported: 3.088 MBit/s, 6.176 MBit/s, 8.192 MBit/s * 32 Bit / 33 MHz PCI 2.1 master/slave interface; this interface can be configured in De-mux mode * Separate Rx and Tx Status Queues in host memory (the MUNICH128X provides one set for each of the four HDLC Controllers) * Slave access to on-chip registers * Time Slot-shift capability: - Programmable from -4 clock edges to +3 clock edges relative to the synchronization pulse - Programmable to sample Tx and/or Rx data at either falling or rising edge of clock * Software initiated action request (via the Command Register) * Tx End-of-Packet transmitted-on-wire interrupt capability for each channel * Tx packet size increased to 64 Kbytes (HDLC mode) * Rx packet size 8 Kbyte limit interrupt disable * Tx data TRISTATETM control line * Synchronized data transfer in TMA mode for complete transparency when using fractional T1/PRI * Little/Big Endian data formats
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Pin Descriptions
2
2.1
*
Pin Descriptions
Pin Diagram
(top view) P-MQFP-160-1
TDI DPCI0 DPCI1 A27 A26 A25 VDD3 VSS A24 A23 A22 A21 A20 VDD3 VSS VDD3 VSS A19 A18 A17 A16 RST VDD3 VSS CLK GNT REQ AD31 AD30 VDD3 VSS AD29 AD28 AD27 AD26 AD25 VDD3 VSS AD24 C/BE3
120 121 124 127 130 133 136 139
TDO TRST VSS VDD3 TMS TCK RxCLK0 RSP0 RxD0 TxDEN0 TxD0 TSP0 TxCLK0 RxCLK1 RSP1 RxD1 VSS VDD3 VDD3 VSS TxDEN1 TxD1 TSP1 TxCLK1 RxCLK2 RSP2 RxD2 TxDEN2 TxD2 TSP2 TxCLK2 RxCLK3 VSS VDD3 RSP3 RxD3 TxDEN3 TxD3 TSP3 TxCLK3 117 114 111 108 105 102 99 96 93 90 87 84 81 80 77 74 71 68 65 62
MUNICH128X
142 145 148 151 154 157 160 1 59 56 53 50 47 44 41 40
4
7
10
13
16
19
22
25
28
31
34
37
W/R A2 VSS VDD3 A3 A4 A5 A6 VSS VDD3 A7 A8 A9 A10 A11 VSS VDD3 VSS VDD3 A12 A13 A14 A15 INTA VSS VDD3 AD0 AD1 AD2 AD3 VSS VDD3 AD4 AD5 AD6 AD7 VSS VDD3 C/BE0 AD8
IDSEL AD23 VDD3 VSS AD22 AD21 AD20 AD19 VDD3 VSS AD18 AD17 AD16 C/BE2 VDD5 VDD5 VDD3 VSS FRAME IRDY TRDY DEVSEL STOP VDD3 VSS PERR SERR PAR C/BE1 AD15 VDD3 VSS AD14 AD13 AD12 AD11 VDD3 VSS AD10 AD9
ITP10331
Figure 2-1
Pin Configuration
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Pin Descriptions Pin descriptions in Tables 2-1 to 2-8 are grouped by functional block, as shown by the heading for that group. Pin types are indicated by abbreviations: Signal Type Definitions: The following signal type definitions are partly taken from the PCI Specification Revision 2.1: I O t/s, I/O s/t/s
Input is a standard input-only signal. Totem Pole Output is a standard active driver. Tri-State or I/O is a bi-directional, tri-state input/output pin. Sustained Tri-State is an active low tri-state signal owned and driven
by one and only one agent at a time. (For further information refer to the PCI Specification Revision 2.1)
o/d
Open Drain allows multiple devices to share as a wire-OR. A pull-up
is required to sustain the inactive state until another agent drives it, and must be provided by the central resource.
Signal Name Conventions: NC
Not Connected Pin Such pins are not bonded with the silicon. Although any potential at these pins will not impact the device it is recommended to leave them unconnected. NC pins might be used for additional functionality in later versions of the device. Leaving them unconnected will guarentee hardware compatibility to later device versions.
Reserved
Reserved pins are for vendor specific use only and should be connected
as recommended to guarantee normal operation.
Note: The signal type definition specifies the functional usage of a pin. This does not reflect necessarily the implementation of a pin, e.g. a pin defined of signal type `Input' may be implemented with a bidirectional pad. Note: All unused input or I/O pins without internal Pull-Up/Down resistor must be connected to a defined level either connected to VDD3 /VSS or to a Pull-Up/Down resistor (<= 10k).
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Pin Descriptions Table 2-1 Pin No. 114 Pin Descriptions by Functional Block: Port 0 Serial Interface Symbol RxCLK0 Type Description I Receive Clock 0 The clock input pin used for sampling the data on RxD0. The MUNICH128X supports the following PCM clock rates; programmed via the MODE1 register: T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz; E1: 2.048 MHz, 4.096 MHz, 8.192 MHz. Receive Data 0 The data input pin which is sampled using RxCLK0. Receive Synchronization Pulse 0 The input pin used for Rx PCM frame synchronization; the synchronization pulse marks the first bit in the PCM frame. Transmit Clock 0 The clock input used for clocking out the data on TxD0. In most applications, the signal that drives this pin is externally connected to RxCLK0. Transmit Data 0 Provides the data which is clocked out of the MUNICH128X by TxCLK0; data is push-pull for active bits in the PCM frame and TRISTATETM for inactive bits. Transmit Synchronization Pulse 0 The input pin used for Tx PCM frame synchronization; the synchronization pulse marks the last bit in the PCM frame. Transmit Data Enable 0 An active low output signal which specifies data on the TxD0 output pin is valid.
112 113
RxD0 RSP0
I I
108
TxCLK0
I
110
TxD0
O
109
TSP0
I
111
TxDEN0
O
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Pin Descriptions Table 2-2 Pin No. 107 Pin Descriptions by Functional Block: Port 1 Serial Interface Symbol RxCLK1 Type Description I Receive Clock 1 The clock input pin used for sampling the data on RxD1 The MUNICH128X supports the following PCM clock rates, programmed via the MODE1 register: T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz; E1: 2.048 MHz, 4.096 MHz, 8.192 MHz. Receive Data 1 The data input pin which is sampled using RxCLK1. Receive Synchronization Pulse 1 The input pin used for Rx PCM frame synchronization; the synchronization pulse marks the first bit in the PCM frame. Transmit Clock 1 The clock input used for clocking out the data on TxD1. In most applications, the signal that drives this pin is externally connected to RxCLK1. Transmit Data 1 Provides the data which is clocked out of the MUNICH128X by TxCLK1; data is push-pull for active bits in the PCM frame and TRISTATETM for inactive bits. Transmit Synchronization Pulse 1 The input pin used for Tx PCM frame synchronization; the synchronization pulse marks the last bit in the PCM frame. Transmit Data Enable 1 An active low output signal which specifies data on the TxD1 output pin is valid.
105 106
RxD1 RSP1
I I
97
TxCLK1
I
99
TxD1
O
98
TSP1
I
100
TxDEN1
O
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Pin Descriptions Table 2-3 Pin No. 96 Pin Descriptions by Functional Block: Port 2 Serial Interface Symbol RxCLK2 Type Description I Receive Clock 2 The clock input pin used for sampling the data on RxD2. The MUNICH128X supports the following PCM clock rates, programmed via the MODE1 register: T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz; E1: 2.048 MHz, 4.096 MHz, 8.192 MHz. Receive Data 2 The data input pin which is sampled using RxCLK2. Receive Synchronization Pulse 2 The input pin used for Rx PCM frame synchronization; the synchronization pulse marks the first bit in the PCM frame. Transmit Clock 2 The clock input used for clocking out the data on TxD2. In most applications, the signal that drives this pin is externally connected to RxCLK2. Transmit Data 2 Provides the data which is clocked out of the MUNICH128X by TxCLK2; data is push-pull for active bits in the PCM frame and TRISTATETM for inactive bits. Transmit Synchronization Pulse 2 The input pin used for Tx PCM frame synchronization; the synchronization pulse marks the last bit in the PCM frame. Transmit Data Enable 2 An active low output signal which specifies data on the TxD2 output pin is valid.
94 95
RxD2 RSP2
I I
90
TxCLK2
I
92
TxD2
O
91
TSP2
I
93
TxDEN2
O
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Pin Descriptions Table 2-4 Pin No. 89 Pin Descriptions by Functional Block: Port 3 Serial Interface Symbol RxCLK3 Type Description I Receive Clock 3 The clock input pin used for sampling the data on RxD3. The MUNICH128X supports the following PCM clock rates, programmed via the MODE1 register: T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz; E1: 2.048 MHz, 4.096 MHz, 8.192 MHz. Receive Data 3 The data input pin which is sampled using RxCLK3. Receive Synchronization Pulse 3 The input pin used for Rx PCM frame synchronization; the synchronization pulse marks the first bit in the PCM frame. Transmit Clock 3 The clock input used for clocking out the data on TxD3. In most applications, the signal that drives this pin is externally connected to RxCLK3. Transmit Data 3 Provides the data which is clocked out of the MUNICH128X by TxCLK3; data is push-pull for active bits in the PCM frame and TRISTATETM for inactive bits. Transmit Synchronization Pulse 3 The input pin used for Tx PCM frame synchronization; the synch. pulse marks the last bit in the PCM frame. Transmit Data Enable 3 An active low output signal which specifies data on the TxD3 output pin is valid.
85 86
RxD3 RSP3
I I
81
TxCLK3
I
83
TxD3
O
82
TSP3
I
84
TxDEN3
O
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Pin Descriptions Table 2-5 Pin No. Pin Descriptions by Functional Block: PCI Interface Symbol Type Description t/s Address/Data Bus A bus transaction consists of an address phase followed by one or more data phases. When MUNICH128X is Master, AD(31:0) are outputs in the address phase of a transaction. During the data phases, AD(31:0) remain outputs for write transactions, and become inputs for read transactions. When MUNICH128X is Slave, AD(31:0) are inputs in the address phase of a transaction. During the data phases, AD(31:0) remain inputs for write transactions, and become outputs for read transactions. AD(31:0) is sampled on the rising edge of CLK. Command/Byte Enable During the address phase of a transaction, C/BE(3:0) define the bus command. During the data phase, C/ BE(3:0) are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. C/BE0 applies to byte 0 (lsb) and C/BE3 applies to byte 3 (msb). When MUNICH128X is Master, C/BE(3:0) are outputs. When MUNICH128X is Slave, C/BE(3:0) are inputs. C/BE(3:0) is sampled on the rising edge of CLK. Parity PAR is even parity across AD(31:0) and C/BE(3:0). PAR is stable and valid one clock after the address phase. PAR has the same timing as AD(31:0) but delayed by one clock. When MUNICH128X is Master, PAR is output during address phase and write data phases. When MUNICH128X is Slave, PAR is output during read data phases. Parity errors detected by the MUNICH128X are indicated on PERR output. PAR is sampled on the rising edge of CLK.
2, 5...8, AD(31:0) 11...13, 30, 33...36, 39...41, 45...48, 51...54, 148, 149, 152...156, 159
14, 29, 42, 160
C/BE(3:0) t/s
28
PAR
t/s
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Pin Descriptions Table 2-5 Pin No. 19 Pin Descriptions by Functional Block: PCI Interface (cont'd) Symbol FRAME Type Description s/t/s Frame FRAME indicates the beginning and end of an access. FRAME is asserted to indicate a bus transaction is beginning. While FRAME is asserted, data transfers continue. When FRAME is deasserted, the transaction is in the final phase. When MUNICH128X is Master, FRAME is an output. When MUNICH128X is Slave, FRAME is an input. FRAME is sampled on the rising edge of CLK. Initiator Ready IRDY indicates the bus master's ability to complete the current data phase of the transaction. It is used in conjunction with TRDY. A data phase is completed on any clock where both IRDY and TRDY are sampled asserted. During a write, IRDY indicates that valid data is present on AD(31:0). During a read, it indicates the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted together. When MUNICH128X is Master, IRDY is an output. When MUNICH128X is Slave, IRDY is an input. IRDY is sampled on the rising edge of CLK. Target Ready TRDY indicates a slave's ability to complete the current data phase of the transaction. During a read, TRDY indicates that valid data is present on AD(31:0). During a write, it indicates the target is prepared to accept data. When MUNICH128X is Master, TRDY is an input. When MUNICH128X is Slave, TRDY is an output. TRDY is sampled on the rising edge of CLK. STOP STOP is used by a slave to request the current master to stop the current bus transaction. When MUNICH128X is Master, STOP is an input. When MUNICH128X is Slave, STOP is an output. STOP is sampled on the rising edge of CLK.
20
IRDY
s/t/s
21
TRDY
s/t/s
23
STOP
s/t/s
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Pin Descriptions Table 2-5 Pin No. 1 Pin Descriptions by Functional Block: PCI Interface (cont'd) Symbol IDSEL Type Description I Initialization Device Select When MUNICH128X is slave in a transaction, if IDSEL is active in the address phase and C/BE(3:0) indicates a Config read or write, the MUNICH128X assumes a read or write to a configuration register. In response, the MUNICH128X asserts DEVSEL during the subsequent CLK cycle. IDSEL is sampled on the rising edge of CLK. Device Select When activated by a slave, it indicates to the current bus master that the slave has decoded its address as the target of the current transaction. If no bus slave activates DEVSEL within six bus CLK cycles, the master should abort the transaction. When MUNICH128X is Master, DEVSEL is input. If DEVSEL is not activated within six clock cycles after an address is output on AD(31:0), the MUNICH128X aborts the transaction and generates an INTA. When MUNICH128X is Slave, DEVSEL is output. Parity Error When activated, indicates a parity error over the AD(31:0) and C/BE(3:0) signals (compared to the PAR input). It has a delay of one CLK cycle with respect to AD and C/BE(3:0) (i.e., it is valid for the cycle immediately following the corresponding PAR cycle). PERR is asserted relative to the rising edge of CLK. System Error The MUNICH128X asserts this signal to indicate a fatal system error. SERR is sampled on the rising edge of CLK. Request Used by the MUNICH128X to request control of the PCI. REQ is sampled on the rising edge of CLK.
22
DEVSEL
s/t/s
26
PERR
s/t/s
27
SERR
o/d
147
REQ
t/s
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Pin Descriptions Table 2-5 Pin No. 146 Pin Descriptions by Functional Block: PCI Interface (cont'd) Symbol GNT Type Description t/s Grant This signal is asserted by the arbiter to grant control of the PCI to the MUNICH128X in response to a bus request via REQ. After GNT is asserted, the MUNICH128X will begin a bus transaction only after the current bus Master has deasserted the FRAME signal. GNT is sampled on the rising edge of CLK. Clock Provides timing for all PCI transactions. Most PCI signals are sampled or output relative to the rising edge of CLK. The maximum CLK frequency is 33 MHz. Reset An active RST signal brings all PCI registers, sequencers and signals into a consistent state. All PCI output signals are driven to their initial state.
145
CLK
I
142
RST
I
57
INTA
O (o/ Interrupt Request d) When an interrupt status is active and unmasked, the MUNICH128X activates this open-drain output. Examples of interrupt sources are transmission/ reception error, completion of transmit or receive packets etc. The MUNICH128X deactivates INTA when the global interrupt status register STAT is read. INTA is activated/deactivated asynchronous to the CLK.
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Pin Descriptions Table 2-6 Pin No. 122, 123 Pin Descriptions by Functional Block: DEMUX Interface (additional signals to PCI Interface) Symbol Type Description PCI/De-multiplexed Mode select DPCI(1:0) = 002 : PCI Mode DPCI(1:0) = 012 : reserved DPCI(1:0) = 102 : PCI/De-multiplexed Mode DPCI(1:0) = 112 : reserved Pins DPCI(1:0) should be connected to VDD3/VSS to achieve the appropriate mode selection. DEMUX Address Bus These pins provide the address bus for the Demultiplexed Interface, when DPCI(1:0) = 102. Note: Pin 124 'A27' provides a buffered PCI clock output signal if configured in PCI operation mode (DPCI(1:0) = '00'). I/O Write/Read This signal distinguishes write and read operations in the De-multiplexed mode. It is tristate when the MUNICH128X is in PCI mode. A Pull-Up resistor to VDD3 is recommended if Demultiplexed mode is not used. DPCI(1:0) I
58...61, A(27:2) 66...70, 73...76, 79, 124...126, 129...133, 138...141
I/O
80
W/R
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Pin Descriptions Table 2-7 Pin No. Pin Descriptions by Functional Block: Power Supply Symbol Type Description Ground (0 V) All pins must have the same reference level.
VSS 4, 10, 18, 25, 32, 38, 44, 50, 56, 63, 65, 72, 78, 88, 101, 104, 118, 128, 135, 137, 144, 151, 158
3, 9, 17, 24, VDD3 31, 37, 43, 49, 55, 62, 64, 71, 77, 87, 102, 103, 117, 127, 134, 136, 143, 150, 157 15, 16
-
Supply Voltage (3.3 V 0.3 V) All pins must have the same reference level.
VDD5
-
Supply Voltage These pins MUST be connected to 5 V supply. The MUNICH128X uses 3.3 V I/O pads that always require additional 5 V supply. The 5 V power supply allows the MUNICH128X I/O pads to provide 5 V input tolerance.
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Pin Descriptions Table 2-8 Pin No. 115 Pin Descriptions by Functional Block: Test Interface Symbol TCK Type Description I JTAG Test Clock A Pull-Up resistor to VDD3 is recommended if boundary scan unit is not used. JTAG Test Mode Select A Pull-Up resistor to VDD3 is recommended if boundary scan unit is not used. JTAG Test Data Input A Pull-Up resistor to VDD3 is recommended if boundary scan unit is not used. JTAG Test Data Output JTAG Reset TRST should be connected to VSS if boundary scan unit is not used.
116
TMS
I
121
TDI
I
120 119
TDO TRST
O I
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Functional Description
3
3.1
Functional Description
Functional Overview
The MUNICH128X provides four independent "cores" as well as global functional blocks (see Figure 3-1).
3.2
*
Block Diagram
PCM - BUS
PCM - BUS
CORE Serial PCM/IF Serial PCM/IF
CORE
Register Set
24/32 Channel
24/32 Channel
Arbiter
64 Channel
64 Channel
Internal
PCI/DEMUX Interface
Address/Data
Control
Register Set
I-BUS
ITB10008
Figure 3-1
Block Diagram
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Functional Description
3.3
Functional Blocks
Each core consists of dedicated circuitry: Serial PCM Interface Controller, Configuration and State RAM (CSR), 24/32-channel HDLC Controller with internal Transmit and Receive Buffers, 64-Channel DMA Controller, and Register Set. 3.3.1 Serial PCM Interface Controller
This block controls both Parallel-to-Serial (Tx) and Serial-to-Parallel (Rx) conversion and PCM timing. Additionally, this block controls the multiplexing of channels through the HDLC controller, as well as switching for the test loops. 3.3.2 Configuration and State RAM (CSR)
This block contains internal RAM which maintains the state of each channel. The Multiplex Control Block of the Serial PCM Interface Controller handles the switching of the CSR information into and out of the 24/32-channel HDLC Controller. 3.3.3 24/32-channel HDLC Controller
The HDLC Controller performs protocol processing for each channel independently, based on the CSR information for each channel.
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Functional Description 3.3.3.1 Tx Block
Transmit Buffer (TB) The Tx Block of the HDLC Controller contains a 1024 byte buffer (TB) which may be allocated to all 32 channels of one cove equally (i.e., 2-DWords per channel) or may be allocated based on superchannel considerations (e.g., 8-DWords per channel for 8 channels). HDLC Protocol Bit stuffing, flag generation, flag stuffing and adjustment, and CRC generation (either 16bit or 32-bit) are performed. V.110 and V.30 Protocol Bit framing from 600 bit/s to 38.4 Kbit/s, automatic generation of the synchronization pattern, generation of loss of synchronization, programmable E/SX bits (including during run-time) are performed. Transparent Mode A This mode supports slot synchronous, transparent transmission without frame structure. It provides flag generation, flag stuffing, flag generation in the abort case with programmable flag, and synchronized data transfer for fractional T1/E1 PRI applications. Transparent Mode B This mode supports transparent transmission in frames delimited by 00H flags, shared closing and opening flag, flag stuffing and flag generation in the abort case. Transparent Mode R This mode supports transparent transmission with GSM 08.60 frame structure with automatic 0000H flag generation and support of 40, 39.5, and 40.5 octet frames. Protocol Independence Channel inversion (data, flags, idle code) follows the format conventions as in CCITT Q.921.
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Functional Description 3.3.3.2 Rx Block
Receive Buffer (RB) The Rx Block of the HDLC Controller contains a 1024 byte buffer (RB) which is allocated to channels via requests from the protocol controller, as determined by the received data for each channel. HDLC Protocol Flag detection (supports multiple flags between packets or a single flag shared as a closing flag and an opening flag between packets), abort character detection, idle code detection, zero-bit detection and deletion, packet length count, and CRC checking (either 16-bit or 32-bit) are performed. V.110 and V.30 Protocol Bit framing from 600 bit/s to 38.4 Kbit/s, automatic synchronization of the synchronization pattern, detection of loss of synchronization, programmable E/SX bits (including during run-time) are performed. Transparent Mode A Mode A supports slot synchronous transparent reception without frame structure. It provides flag detection, flag extraction and synchronized data transfer for fractional T1/ E1 PRI applications. Transparent Mode B This mode supports transparent reception in frames delimited by 00H flags. Sharing closing flag and opening flag, and flag detection. Transparent Mode R This mode supports transparent reception with GSM 08.60 frame structure with automatic 0000H flag detection. Support of 40, 39.5, and 40.5 octet frames, and error detection (non-octet frame contents, short frame, long frame). Protocol Independence Channel inversion (data, flags, idle code) follows the format conventions as in CCITT Q.921, data overflow and underflow detection.
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Functional Description 3.3.3.3 64-channel DMA Controller Block
This block controls memory address calculation, buffer management (including linkedlists) and interrupt processing. The 24/32-channel HDLC Controller has a dedicated DMA channel for each channel and direction. During run-time, the DMA Controller performs operations with host memory primarily as a bus master. This block provides 32 input and 32 output channels. 3.3.3.4 Register Set
This block provides configuration and control of the Serial PCM Interface Controller, the HDLC Controller and the DMA Controller. Also, a shared status register STAT provides status and interrupt information associated with each of the four cores.
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Functional Description 3.4 Global Functional Blocks
The MUNICH128X provides global functional blocks for the Internal Bus, Arbiter, and 32 Bit / 33 MHz PCI 2.1 Interface as well as De-multiplexed Bus Interface Controller. 3.4.1 Internal Bus
This block of the MUNICH128X interfaces the Bus Interface Controller to the four DMA Controllers. This is a 33 MHz, 32 Bit demultiplexed bus that operates in a synchronous, non-burst manner for data transfers and operates in a synchronous burst manner for descriptor transfers. 3.4.2 Arbiter
The Arbiter provides access control of the Internal Bus. A "round-robin" Arbiter is used which provides "fairness" for the four master DMA controllers. 3.4.3 32 Bit / 33 MHz Bus Interface Controller
The MUNICH128X may be configured either for 32 Bit / 33 MHz PCI bus operation or for a 32 Bit / 33 MHz De-multiplexed bus interface. The MUNICH128X input pins DPCI(1:0) are used to select the desired configuration. The De-multiplexed bus interface is a synchronous interface very similar to the PCI interface with the following exceptions: 1. The W/R input/output signal replaces the function of the PCI command nibble of the C/BE(3:0) bit field. 2. Note, that in DEMUX mode as in PCI mode the MUNICH128X provides only the first address of a Master burst read or write transaction. If burst transactions are not supported by the local bus environment, burst capability can be disabled by bit DBE in the global configuration register (CONF).
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Functional Description
3.5
System Integration
The MUNICH128X provides protocol processing and host memory buffer management for four independent T1/E1 PRI ports. As such, the MUNICH128X fits into a system between the framer or LIU/framer devices (e.g., the Siemens FALC(R)54/FALC(R)54-LH transceiver) and the host bus (e.g. PCI Bus), as illustrated in Figure 3-1. The MUNICH128X provides four independent Serial PCM ports which connect directly into the framer devices. In PCI based systems a dedicated microcontroller or PCI bridge chip is necessary to configure the framer or LIU/framer devices. Additionally, the MUNICH128X provides a PCI 2.1 interface which connects directly to the system PCI bus. Optionally, this bus can be configured in De-multiplexed Mode.
T1/E1/PRI
T1/E1/PRI
T1/E1/PRI
T1/E1/PRI
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
Dedicated CPU
MUNICH128X
PCI BUS
PCI Bridge Chip
Host Memory
Processor
ITS10009
Figure 3-1
System Integration of the MUNICH128X in PCI-Based System
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Functional Description
T1/E1/PRI
T1/E1/PRI
T1/E1/PRI
T1/E1/PRI
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
FALC 54 / R FALC -LH Transceiver
R
MUNICH128X
Glue Logic
De-multiplexed BUS
Processor
Host Memory
ITS10010
Figure 3-2
System Integration of the MUNICH128X in De-multiplexed System
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Operational Description
4
4.1
Operational Description
Operational Overview
The MUNICH128X is a "channelized" WAN protocol controller that performs protocol processing on up to 128 full duplex serial PCM channels. It performs HDLC-based layer 2 protocol formatting and deformatting, as well as rate adaptation, for each of the 128 channels independently. The MUNICH128X provides dedicated registers for each of the four HDLC controllers, with each set similar to the "core" registers of the MUNICH32X. Software developed for the "core" of the MUNICH32X requires minimal modification to run optimally on the MUNICH128X. The architecture of the register sets allows any number of HDLC controllers within an MUNICH128X device to operate with host software images that differ only in their offset from the PCI base address and their pointers into host memory. Host software sets the operating mode, rate adaptation method and time slot assignment of each channel by configuring "blocks" (CCBs) within host memory. During "run-time" the MUNICH128X performs all data and descriptor transfers as a bus master. Additionally, host software may access any register of a particular HDLC Controller within the MUNICH128X, with the device acting as a bus slave. The MUNICH128X provides a single Status Register, which maintains information of all interrupt events for the controller.
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Electrical Characteristics
5
5.1
Electrical Characteristics
Important Electrical Requirements
VDD3 max = 3.6 V VDD5 max = 5.25 V
VDD3 = 3.3 V 0.3 V VDD5 = 5.0 V 0.25 V
During all MUNICH128X power-up and power-down situations the difference |VDD5 - VDD3| may not exceed 3.6V. The absolute maximums of VDD5 and VDD3 should never be exceeded. Figure 5-1 shows that both VDD3 and VDD5 can take on any time sequence not exceeding a voltage difference of 3.6V, for up to 50 milliseconds at power-up and powerdown.Within 50 milliseconds of power-up the voltages must be within their respective absolute voltage limits. At power-down, within 50 milliseconds of either voltage going outside its operational range, the voltage difference should not exceed 3.6V and both voltages must be returned below 0.1V:
power up U/V VDD5 limit VDD5 limit power down
5V +/- 0.25V
3.3V +/- 0.3V
VDD3 limit
VDD3 limit
0.1V 0 50 N N+50 t/ms
Within the grey boxes any shape of VDD3 and VDD5 signal is allowed with the requirements that the absolute limits of each signal are not exceeded, the slew rate recommendation for VDD3 is met to guarantee proper boundary scan reset and the voltage difference does not exceed 3.6V. Outside the grey boxes the voltages provided to VDD3 and VDD5 should be inside the normal operation range. In this power-up example VDD5 is enabled after VDD3 reached its minimum operation value which is a typical implementation. For power-down VDD5 is switched off before VDD3.
Figure 5-1
Power-up and Power-down scenarios
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Electrical Characteristics Similar criteria also apply to power down in case of power failure situations:
U/V
power failure: VDD5 break down VDD5 limit
U/V
power failure: VDD3 break down VDD5 limit
5V +/- 0.25V
5V +/- 0.25V
VDD3 limit 3.3V +/- 0.3V 3.3V +/- 0.3V
VDD3 limit
0.1V 0 N 50
0.1V t/ms 0 N N+15 t/ms
Within the grey boxes any shape of VDD3 and VDD5 signal is allowed with the requirements that the absolute limits of each signal are not exceeded and the specified voltage differences are not exceeded. a. In case of VDD5 break-down the 3.6V difference is not exceeded anyway. The voltages must return below 0.1V within 50 milliseconds. b. In case of VDD3 break-down the maximum voltage difference must not exceed 4.5 V for a maximum of 15 milliseconds.The voltages must return below 0.1V within 50 milliseconds. This scenario is allowed for 2000 power failure cycles.
Figure 5-2
Power-Failure scenarios
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Electrical Characteristics
5.2
Absolute Maximum Ratings Absolute Maximum Ratings Symbol min. Limit Values max. C 0 -40 70 85 125 - 65 - 0.4 125 C C V V Unit
Table 5-1 Parameter
Ambient temperature under bias PEB PEF Junction temperature under bias Storage temperature Voltage at any pin with respect to ground ESD robustness1) HBM: 1.5 k, 100 pF
1)
TA
TJ Tstg VS
VESD,HBM
VDD5 + 0.4
1000
According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993. The RF Pins 20, 21, 26, 29, 32, 33, 34 and 35 are not protected against voltage stress > 300 V (versus VS or GND). The high frequency performance prohibits the use of adequate protective structures.
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
5.3
Table 5-2 Parameter
Thermal Package Characteristics
Thermal Package Characteristics Symbol Ambient Temperature: TA=+25C JA(0,25) 29 C/W Value Unit
Thermal Package Resistance Junction to Ambient Airflow: without airflow
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Electrical Characteristics
5.4
Parameter
Operating Range
Symbol Limit Values min. max. C 0 -40 70 85 3.6 5.25 0 V V V Unit Test Condition
Ambient temperature PEB PEF Supply voltage VDD3 Supply voltage VDD5 Ground
TA
VDD3 VDD5 VSS
3.0 4.75 0
Note: In the operating range, the functions given in the circuit description are fulfilled.
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Electrical Characteristics
5.5
DC Characteristics
a) Non-PCI Interface Pins Table 5-3 Parameter L-input voltage H-input voltage L-output voltage Non-PCI Interface Pins TA = 0 to + 70C; VDD5 = 5 V 5%, VDD3 = 3.3 V 0.3 V, VSS = 0 V Symbo Limit Values l min. max. Unit Test Condition V V
VIL VIH VQL
- 0.4 2.0
0.8 0.45
VDD5 + 0.4 V IQL = 7 mA
(pin TXD) IQL = 2 mA (all others / non-PCI)
H-output voltage Power supply current
VQH operational ICC3 power down ICC3
(no clocks)
2.4 < 300 <5
V mA mA
IQH = - 400 A VDD3 = 3.3 V,
VDD5 = 5.0 V, inputs at 0 V/VDD3, no output loads
ICC5 power down ICC5
operational (no clocks)
<1 <1
mA mA
VDD3 = 3.3 V,
VDD5 = 5.0 V, inputs at 0 V/VDD3, no output loads
ICC3Peak
Peak Power supply current during ICC5Peak RAM initialization process
< 700 < 10
mA mA
VDD3 = 3.3 V,
VDD5 = 5.0 V, inputs at 0 V/VDD3, no output loads, 300 PCI clocks after power-up 0 V < VIN < VDD to 0 V 0 V < VOUT < VDD to 0 V
Input leakage current Output leakage current
ILI ILQ
10
A
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Note: The electrical characteristics described in section 5.2 also apply here!
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Electrical Characteristics b) PCI Pins According to the PCI specification V2.1 from June 1, 1995 (Chapter 4: Electrical Specification for 5 V signalling)
Note: According the electrical characteristics all DEMUX Interface pins (DPCI(1:0), A(27:2), W/R) are treated as PCI Interface pins.
5.6
Capacitances
a) Non-PCI Interface Pins Table 5-4 Parameter Input capacitance Output capacitance I/O-capacitance b) PCI Pins According to the PCI specification V2.1 from June 1, 1995 (Chapter 4: Electrical Specification for 5 V signalling) Non-PCI Interface Pins TA = 25C; VDD5 = 5 V 5%, VDD3 = 3.3 V 0.3 V, VSS = 0 V Symbol Limit Values min. max. 5 10 15 pF pF pF 1 5 6 Unit Test Condition
CIN COUT CIO
Note: According the electrical characteristics all DEMUX Interface pins DPCI(1:0), A(27:2), W/R) are treated as PCI Interface pins.
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5.7
AC Characteristics
a) Non-PCI Interface Pins
TA = 0 to + 70C; VDD5 = 5 V 5%; VDD3 = 3.3 V 0.3 V
Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at 2.0 V for a logical "1" and at 0.8 V for a logical "0". The AC testing input/output waveforms are shown below.
2.4 2.0 Test Points 0.8 0.45 0.8 2.0 Device Under Test
C Load = 50 pF
ITS09800
Figure 5-1 b) PCI Pins
Input/Output Waveform for AC Tests
According to the PCI specification V2.1 from June 1, 1995 (Chapter 4: Electrical Specification for 5 V signalling)
Note: According the electrical characteristics all DEMUX Interface pins DPCI(1:0), A(27:2), W/R) are treated as PCI Interface pins.
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5.7.1
PCI Bus Interface Timing
The AC testing input/output waveforms are shown in figures 5-2 and 5-3 below.
Clock
Vth Vtl
Vtest t val
Output Delay
Vtest t off t on
Device Under Test
C Load = 50 pF
TRI-STATE Output
Vtest
Vtest
ITS09801
Figure 5-2
PCI Output Timing Measurement Waveforms
Figure 5-3 Table 5-5 Symbol
PCI Input Timing Measurement Waveforms PCI Input and Output Measurement Conditions Value 2.4 0.4 1.5 2.0 Unit V V V V
Vth Vtl Vtest Vmax
The timings below show the basic read and write transaction between an initiator (Master) and a target (Slave) device. The MUNICH128X is able to work both as master and slave.
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Electrical Characteristics As a master the MUNICH128X reads/writes data from/to host memory using DMA and burst. The slave mode is used by an CPU to access the MUNICH128X PCI Configuration Space and the on-chip registers.
5.7.1.1
PCI Read Transaction
The transaction starts with an address phase which occurs during the first cycle when FRAME is activated (clock 2 in figure 5-4). During this phase the bus master (initiator) outputs a valid address on AD(31:0) and a valid bus command on C/BE(3:0). The first clock of the first data phase is clock 3. During the data phase C/BE indicate which byte lanes on AD(31:0) are involved in the current data phase. The first data phase on a read transaction requires a turn-around cycle. In figure 5-4 the address is valid on clock 2 and then the master stops driving AD. The target drives the AD lines following the turnaround when DEVSEL is asserted. (TRDY cannot be driven until DEVSEL is asserted.) The earliest the target can provide valid data is clock 4. Once enabled, the AD output buffers of the target stay enabled through the end of the transaction. A data phase may consist of a data transfer and wait cycles. A data phase completes when data is transferred, which occurs when both IRDY and TRDY are asserted. When either is deasserted a wait cycle is inserted. In the example below, data is successfully transferred on clocks 4, 6 and 8, and wait cycles are inserted on clocks 3, 5 and 7. The first data phase completes in the minimum time for a read transaction. The second data phase is extended on clock 5 because TRDY is deasserted. The last data phase is extended because IRDY is deasserted on clock 7. The Master knows at clock 7 that the next data phase is the last. However, the master is not ready to complete the last transfer, so IRDY is deasserted on clock 7, and FRAME stays asserted. Only when IRDY is asserted can FRAME be deasserted, which occurs on clock 8.
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Electrical Characteristics
CLK 1 FRAME 2 3 4 5 6 7 8 9
AD
Address
Data 1
Data 2
Data 3
C/BE
Bus CMD
BE's
Data Transfer
Data Transfer
TRDY
DEVSEL Address Phase Data Phase Data Phase Bus Transaction Data Phase
ITD07575
Figure 5-4
PCI Read Transaction
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Data Transfer
IRDY
Wait
Wait
Wait
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5.7.1.2
PCI Write Transaction
The transaction starts when FRAME is activated (clock 2 in figure 5-5). A write transaction is similar to a read transaction except no turnaround cycle is required following the address phase. In the example, the first and second data phases complete with zero wait cycles. The third data phase has three wait cycles inserted by the target. Both initiator and target insert a wait cycle on clock 5. In the case where the initiator inserts a wait cycle (clock 5), the data is held on the bus, but the byte enables are withdrawn. The last data phase is characterized by IRDY being asserted while the FRAME signal is deasserted. This data phase is completed when TRDY goes active (clock 8).
CLK 1 FRAME 2 3 4 5 6 7 8 9
AD
Address
Data 1
Data 2
Data 3
C/BE
Bus CMD
BE's-1
BE's-2
BE's-3
Data Transfer
Data Transfer
TRDY
DEVSEL Address Phase Data Phase Data Phase Bus Transaction
ITD07576
Data Phase
Figure 5-5
PCI Write Transaction
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Data Transfer
IRDY
Wait
Wait
Wait
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5.7.1.3
PCI Timing Characteristics
When the MUNICH128X operates as a PCI Master (initiator) and it either reads or writes a burst - as controlled by the on-chip DMA controller - it does not deactivate IRDY between consecutive data. In other words, no wait states are inserted by the MUNICH128X as a transaction initiator. The numbers of wait states, inserted by the MUNICH128X as initiator are listed in table 5-6. Table 5-6 Transaction 1st Data Cycle Memory read burst Memory write burst Fast Back-to-back burst; 1st transaction Fast Back-to-back burst; 2nd and subsequent transactions 0 0 0 1 Number of Wait States Inserted by the MUNICH128X as Initiator Number of Wait States 2nd and Subsequent Data Cycles 0 0 0 0
When the MUNICH128X operates as a PCI Slave (target), it inserts wait cycles by deactivating TRDY. The numbers of wait states, typically inserted by the MUNICH128X are listed in table 5-6: Table 5-7 Transaction Configuration read Configuration write Register read Register write LBI read LBI write Number of Wait States Inserted by the MUNICH128X as Slave Number of Wait States 2 0 3 0 3 0
The number of wait states inserted by the MUNICH128X as target is not critical because accesses to the MUNICH128X are usually kept to a minimum in a system.
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Electrical Characteristics
tH
tL
2.4 V 2.0 V 1.5 V 0.8 V 0.4 V
Voltage (V)
2 Vpp min
T
ITD07577
Figure 5-6 Table 5-8 Parameter
PCI Clock Specification PCI Clock Characteristics Symbol min. Limit Values typ. max. ns ns ns 4 V/ns 30 11 11 1 Unit
CLK cycle time CLK high time CLK low time CLK slew rate (see note)
T tH
tL
Note: Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in figure 5-6.
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Table 5-9 Parameter
PCI Interface Signal Characteristics Limit Values min. typ. max. 11 12 (3) 20 7 10 0 ns ns ns ns ns ns ns Note 2 Note 2 Notes 1, 2 Notes 1, 2 (2) (2) 2 Unit Remarks
CLK to signal valid delay bussed signals CLK to signal valid delay point-to-point Float to active delay Active to float delay Input setup time to CLK bussed signals Input setup time to CLK point-to-point Input hold time from CLK
Note 1Minimum times are measured with 0 pF equivalent load; maximum times are measured with 50 pF equivalent load. Note 2REQ and GNT are point-to-point signals. All other signals are bussed GNT setup (min) time: 10ns
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Electrical Characteristics
5.7.2
De-multiplexed Bus Interface
CLK
FRAME
D (31 : 0)
Address dont care
Data
Address dont care
Data
A (31 : 2)
Address
Address
BE (3 : 0)
BE (3 : 0)
BE (3 : 0)
W/R
READ Access
WRITE Access
TRDY
ITT10451
Figure 5-7
Master Single READ Transaction followed by a Master Single WRITE Transaction in De-multiplexed Bus Configuration
CLK
FRAME
D (31 : 0)
Address dont care
Data 1
Data 2
Data 3
Data 4
A (31 : 2)
Address
BE (3 : 0)
BE (3 : 0)
BE (3 : 0)
BE (3 : 0)
BE (3 : 0)
W/R
WRITE/READ Access
TRDY
ITT10452
Figure 5-8
Master Burst WRITE/READ Access in De-multiplexed Bus Configuration
The timing provided in Table 5-7 and Table 5-8 can also be applied to the de-multiplexed bus interface.
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Electrical Characteristics Table 5-10 Parameter min. CLK to address bus signal valid delay CLK to W/R signal valid delay Address bus Input setup time to CLK 8 Additional De-multiplexed Interface Signal Characteristics Limit Values typ. max. 12 12 ns ns ns ns ns ns Unit Remarks
Address bus Input hold time 0 to CLK W/R signal Input setup time 8 to CLK W/R signal Input hold time to CLK 0
Note: The PCI parity signal PAR is not generated in de-multiplexed mode. It is driven active low by the MUNICH128X.
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Electrical Characteristics
5.7.3
PCM Serial Interface Timing
37 39
RSP
43 42
RxCLK
38 40 41
RxD
44
46
TSP
50 49
TxCLK
45 47 48
TxD
51
TDTRI
ITT10012
Figure 5-9
PCM Serial Interface Timing
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Electrical Characteristics Table 5-11 No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 PCM Serial Interface Timing Limit Values min. Receive strobe guard time Receive strobe setup Receive strobe hold Receive data setup Receive data hold Receive clock high width Receive clock low width Transmit strobe guard time Transmit strobe setup Transmit strobe hold Transmit data delay Transmit clock to high impedance Transmit clock high width Transmit clock low width Transmit tristate delay 30 30 25 10 5 5 5 5 30 30 20 5 5 25 25 max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Parameter
Note: The frequency on the serial line must be smaller or equal to 1 th /8 of the frequency on the P bus for 1.536 MHz, 1.544 MHz, 2.048 MHz 1 th /4 of the frequency on the P bus for 4.096 MHz. Note: For complete internal or complete external loop t42 and t49 must be greater or equal to 3 times T.
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Electrical Characteristics
5.7.4
System Interface Timing
RES
57
ITD10332
Figure 5-10 System Interface Timing Table 5-12 No. 57 System Interface Timing Limit Values min. RESET pulse width 4 CLK cycles max. Unit
Parameter
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5.7.5
JTAG-Boundary Scan Timing
58 59 60
TCK
61 62
TMS
63 64
TDI
65
TDO
ITD09802
Figure 5-11 JTAG-Boundary Scan Timing Table 5-13 JTAG-Boundary Scan Timing Limit Values min. 58 59 60 61 62 63 64 65 TCK period TCK high time TCK low time TMS setup time TMS hold time TDI setup time TDI hold time TDO valid delay 166 80 80 30 10 30 30 60 max. ns ns ns ns ns ns ns ns Unit
No. Parameter
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Test Modes
6
6.1
Test Modes
Boundary Scan Unit
In the MUNICH128X a Test Access Port (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary scan, meet the requirements given by the JTAG standard: IEEE 1149.1. Figure 6-1 gives an overview.
Test Access Port TCK CLOCK BS Data IN Clock Generation CLOCK TRST Reset TAP Controller Test Control TDI Data in - Finite State Machine - Instruction Register (3 bit) - Test Signal Generator Control Bus 6 ID Data out 1 2 Identification Scan (32 bit) . . .
Pins
TMS
Boundary Scan (n bit) n
. . .
TDO Enable Data out
SS Data out
Figure 6-1
Block Diagram of Test Access Port and Boundary Scan
If no boundary scan operation is planned TRST has to be connected with VSS. TMS and TDI do not need to be connected since pull-up transistors ensure high input levels in this case. Nevertheless it would be a good practice to put the unused inputs to defined levels. In this case, if the JTAG is not used: TMS = TCK = '1' is recommended. Test handling (boundary scan operation) is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, i.e. TRST is connected to VDD or it remains unconnected due to its internal pull-up. Test data at TDI are loaded with a 4-MHz clock
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Test Modes signal connected to TCK. `1' or `0' on TMS causes a transition from one controller state to another; constant '1' on TMS leads to normal operation of the chip.
Table 6-1 TDI -> Seq. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin
Boundary Scan Sequence in MUNICH128X
I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O
Number of Boundary Scan Cells 1 1 3 3 3 3 3 3 3 3 3 3 3 3 3 1 3 3 3 3 3 3 3 3 3
58
Constant Value In, Out, Enable 0 0 011 000 000 100 000 001 000 010 000 110 000 000 000 0 000 000 000 000 000 000 000 000 000
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DPCI0 DPCI1 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 RST CLK GNT REQ AD31 AD30 AD29 AD28 AD27 AD26 AD25
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Test Modes Seq. No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Pin AD24 C/BE3 IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP PERR SERR PAR C/BE1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 C/BE0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Number of Boundary Scan Cells 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Constant Value In, Out, Enable 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
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Test Modes Seq. No. 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 Pin AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 INTA A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 WR TCLK3 TSP3 TD3 TDEN3 RD3 RSP3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I I Number of Boundary Scan Cells 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 1 3 3 1 1 Constant Value In, Out, Enable 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 0 0 000 000 0 0
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Test Modes Seq. No. 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Pin RCLK3 TCLK2 TSP2 TD2 TDEN2 RD2 RSP2 RCLK2 TCLK1 TSP1 TD1 TDEN1 RD1 RSP1 RCLK1 TCLK0 TSP0 TD0 TDEN0 RD0 RSP0 RCLK0 -> TDO I/O I I I I/O I/O I I I I I I/O I/O I I I I I I/O I/O I I I Number of Boundary Scan Cells 1 1 1 3 3 1 1 1 1 1 3 3 1 1 1 1 1 3 3 1 1 1 Constant Value In, Out, Enable 0 0 0 000 000 0 0 0 0 0 000 000 0 0 0 0 0 000 000 0 0 0
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note that some output and input pins of the MUNICH128X are tested as I/O pins in boundary scan, hence using three cells. The boundary scan unit of the MUNICH128X contains a total of n = 275 scan cells. The right column of Table 6-1 gives the initialization values of the cells.
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Test Modes The desired test mode is selected by serially loading a 3-bit instruction code into the instruction register via TDI (LSB first); see Table 6-2. Table 6-2 000 001 010 011 111 others Boundary Scan Test Modes Test Mode EXTEST (external testing) INTEST (internal testing) SAMPLE/PRELOAD (snap-shot testing) IDCODE (reading ID code) BYPASS (bypass operation) handled like BYPASS
Instruction (Bit 2 ... 0)
EXTEST is used to examine the interconnection of the devices on the board. In this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values (`0' or `1', according to Table 6-1). Then the contents of the boundary scan is shifted to TDO. At the same time the next scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. INTEST supports internal testing of the chip, i.e. the output pins capture the current level on the corresponding internal line whereas all input pins are held on constant values (`0' or `1', according to Table 6-1). The resulting boundary scan vector is shifted to TDO. The next test vector is serially loaded via TDI. Then all input pins are updated for the following test cycle.
Note: In capture IR-state the code `001' is automatically loaded into the instruction register, i.e. if INTEST is wanted the shift IR-state does not need to be passed.
SAMPLE/PRELOAD is a test mode which provides a snap-shot of pin levels during normal operation. IDCODE: A 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to `1'. TDI -> 0011 0000 0000 0100 0100 0000 1000 001 1 -> TDO
Note: Since in test logic reset state the code `011' is automatically loaded into the instruction register, the ID code can easily be read out in shift DR state which is reached by TMS = 0, 1, 0, 0.
BYPASS: A bit entering TDI is shifted to TDO after one TCK clock cycle.
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Package Outlines
7
*
Package Outlines
P-MQFP-160-1 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Hardware Reference Manual 63
Dimensions in mm 04.99
GPM05247

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